The present invention relates to a method of designing clock wiring and an apparatus for designing clock wiring for, example, an LSI, PWB or the like.
In the conventional method of designing clock wiring, among the automatic layout tools, stress has been laid on the reduction of clock skew among the automatic layout tool and the shortening of the path length of the worst case path to shorten the path delay time in order to design the layout and wiring, and after the layout is completed, the clock wiring has not specifically been modified. In particular, if it is necessary to shorten the clock cycle, instead of modifying the clock cycle, the path length of the worst case path has been manually shortened to modify the layout or wiring.
FIG. 1 is an example of a layout result of a conventional clock wiring system, in which clock drivers (depicted by "C.D." in the drawing) 201 through 203, flip-flops (F.F.) 204 through 206 operating by the rise of the clock, gates (G) 207 through 211, clock nets 212 through 214 and each net on paths 215, 216 are interconnected so that the clock skew becomes small and the delay time through the path is shortened.
Here, the clock nets 212 through 214 are wired at equal lengths and the clock skew is zero, and the paths 215, 216 are also wired with the shortest route. Let us assume that, according to the result obtained by a delay analysis, the path 215 comprises a delay time of 10 [ns] and is the worst case path smallest in the delay time margin, and the delay time for its next stage path 216 is 6 [ns].
FIG. 2 is a timing chart of the input waveform and the output waveform at the input terminals H01, H02 and H03 of flip-flops 204, 205, 206 and the input waveform at the clock input terminals CK1, CK2, CK3 of the flip-flops 204, 205, 206 when the cycle of the clock generated from the clock drivers 201 through 203 as shown in FIG. 1. Incidentally, let us assume that the set up time of the flip-flops 204, 205, 206 is zero and also that the waveform is free of any rounding.
As illustrated in FIG. 2, the output waveform of the output terminal N01 of the flip-flop 204 is applied to the input terminal H02 of the flip-flop 205 with a delay of 10 [ns], and is taken into the flip-flop 205 when the clock applied to the clock input terminal CK2 rises. Further, the output waveform of the output terminal N02 of the flip-flop 205 is applied to the input terminal H03 with a delay of 6 [ns], and is taken into the flip-flop 206 when the clock applied to the clock input terminal CK3 rises.
Therefore, since the delay time of the path 215 comprises 10 [ns], if the clock cycle is made smaller than 10 [ns], then the flip-flop 205 takes in the state of the input terminal H02 before the state change at the output terminal N01 of the flip-flop 204 propagates to the input terminal H02 making it impossible to achieve normal operation. That is, if the layout and the wiring are carried out according to the conventional clock wiring system, then the clock cycle can be limited by the worst case path with the longest delay time and, further, if the work for shortening the delay time of the worst case path is manually carried out, it can call for a great number of man-days. In particular, as the circuit becomes large-scale, in order to improve its performance, its modifying work also tends to increase, which in turn abruptly increases the number of man-days required for it.